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| [[File:Siliziumwafer.JPG|thumb|250px|Polished 12" and 6" silicon wafers. The notch in the left wafer and the flat cut into the right wafer indicates its crystallographic orientation (see below)]]
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| [[Image:ICC 2008 Poland Silicon Wafer 1 edit.png|thumb|250px|[[VLSI]] microcircuits fabricated on a {{convert|12|in|mm|adj=on}} silicon wafer, before [[wafer dicing|dicing]] and [[Integrated circuit packaging|packaging]]]]
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| In [[electronics]], a '''wafer''' (also called a '''slice''' or '''[[Substrate_(electronics)|substrate]]'''<ref>
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| {{cite book
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| | title = Comprehensive dictionary of electrical engineering
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| | edition = 2nd
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| | author = Phillip A. Laplante
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| | publisher = CRC Press
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| | year = 2005
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| | isbn = 978-0-8493-3086-5
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| | page =
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| | url = http://books.google.com/books?id=_UBzZ4coYMkC&pg=PA739
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| }}</ref>) is a thin slice of [[semiconductor material]], such as a [[Monocrystalline silicon|silicon crystal]], used in the [[Semiconductor fabrication|fabrication]] of [[integrated circuits]] and other microdevices. The wafer serves as the [[substrate (semiconductor)|substrate]] for [[microelectronic]] devices built in and over the wafer and undergoes many [[microfabrication]] process steps such as [[doping (semiconductors)|doping]] or [[ion implantation]], [[Etching (microfabrication)|etching]], [[Thin-film deposition|deposition]] of various materials, and [[Photolithography|photolithographic]] patterning. Finally the individual microcircuits are separated ([[wafer dicing|dicing]]) and [[Integrated circuit packaging|packaged]].
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| Several types of [[solar cell]] are also made from such wafers. On a ''solar wafer'' a solar cell (usually square) is made from the entire wafer.
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| ==Formation==
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| {{See also|Ingot}}
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| [[Image:Czochralski Process.svg|thumb|right|350px|The [[Czochralski process]].]]
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| [[Image:Wafer 2 Zoll bis 8 Zoll 2.jpg|thumb|right|200px|{{convert|2|in|mm|adj=on}}, {{convert|4|in|mm|adj=on}}, {{convert|6|in|mm|adj=on}}, and {{convert|8|in|mm|adj=on}} wafers]]
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| Wafers are formed of highly pure (99.9999999% purity),<ref>"Semi" SemiSource 2006: A supplement to Semiconductor International. December 2005. Reference Section:
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| ''How to Make a Chip.'' Adapted from Design News. Reed Electronics Group.</ref>
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| nearly defect-free single [[crystalline]] material.<ref>SemiSource 2006: A supplement to Semiconductor International. December 2005. Reference Section:
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| ''How to Make a Chip.'' Adapted from Design News. Reed Electronics Group.
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| </ref> One process for forming crystalline wafers is known as [[Czochralski process|Czochralski growth]] invented by the Polish chemist [[Jan Czochralski]]. In this process, a cylindrical [[ingot]] of high purity monocrystalline semiconductor, such as [[monocrystalline silicon|silicon]] or [[germanium]], is formed by pulling a [[seed crystal]] from a '[[Zone melting|melt]]'.<ref>{{cite book |title=Microelectronic Materials and Processes |last=Levy |first=Roland Albert |year=1989 |pages=1–2 |isbn=0-7923-0154-4 |url=http://books.google.com/books?id=wZPRPU6ne7UC&pg=PA248#PPA6,M1 |accessdate=2008-02-23}}</ref><ref name=Grover/> Donor impurity atoms, such as [[boron]] or [[phosphorus]] in the case of silicon, can be added to the molten [[Intrinsic semiconductor|intrinsic]] material in precise amounts in order to [[Doping (semiconductor)|dope]] the crystal, thus changing it into [[N-type semiconductor|n-type]] or [[P-type semiconductor|p-type]] [[extrinsic semiconductor]].
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| The [[ingot]] is then [[wikt:sliced|sliced]] with a wafer saw ([[wire saw]]) and [[polishing|polished]] to form wafers.<ref>{{cite book |last=Nishi |first=Yoshio |year=2000|title=Handbook of Semiconductor Manufacturing Technology |pages=67–71 |publisher=CRC Press |isbn=0-8247-8783-8 |url=http://books.google.com/books?id=Qi98H-iTgLEC&pg=PA70&dq=wafer+flat+and+notch#PPA71,M1 |accessdate=2008-02-25}}</ref> The size of wafers for photovoltaics is 100–200 mm square and the thickness is 200–300 μm. In the future, 160 μm will be the standard.<ref>http://www.omron-semi-pv.eu/en/wafer-based-pv/wafer-preparation/slicing-the-ingot.html</ref> Electronics use wafer sizes from 100–450 mm diameter. (The largest wafers made have a diameter of 450 mm but are not yet in general use.)
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| == Cleaning, texturing and etching ==
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| Wafers are cleaned with [[weak acid]]s to remove unwanted particles, or repair damage caused during the sawing process. When used for [[solar cell]]s, the wafers are textured to create a rough surface to increase their efficiency. The generated PSG ([[phosphosilicate glass]]) is removed from the edge of the wafer in the [[etching]].<ref>http://www.omron-semi-pv.eu/en/wafer-based-pv/front-end/wet-process.html</ref>
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| ==Wafer properties==
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| ===Standard wafer sizes===
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| [[File:Wafers on the conveyor (3347741252).jpg|thumb|Solar wafers on the conveyor]]
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| [[File:Solar World wafer (3347743800).jpg|thumb|Completed solar wafer]]
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| Silicon wafers are available in a variety of diameters from 25.4 mm (1 inch) to 300 mm (11.8 inches).<ref>{{Cite web |title=Silicon Wafer |url=http://www.semiwafer.com/products/silicon.htm |accessdate=2008-02-23}}</ref> [[Semiconductor fabrication plant]]s (also known as ''fabs'') are defined by the diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab considered to be {{nowrap|300 mm}} (12 inch), with the next standard projected to be {{nowrap|450 mm}} (18 inch).<ref>[http://www.intel.com/pressroom/archive/releases/20080505corp.htm Intel, Samsung, TSMC reach agreement about 450mm tech]</ref><ref>[http://www.itrs.net/Links/2008Summer/Public Presentations/PDF/FEP.pdf ITRS Presentation (PDF)]</ref> [[Intel]], [[TSMC]] and [[Samsung]] are separately conducting research to the advent of {{nowrap|450 mm}} "[[prototype]]" (research) [[fab (semiconductors)|fab]]s by 2012, though serious hurdles remain. Dean Freeman, an analyst with [[Gartner Inc.]], predicted that production fabs could emerge sometime between the 2017 and 2019 timeframe,<ref>[http://www.eetimes.com/electronics-news/4079657/Industry-agrees-on-first-450-mm-wafer-standard Industry Agrees on first 450-mm wafer standard - EETimes.com], retrieved on October 22, 2008.</ref> a lot of that will depend on a plethora of new technological breakthroughs and not simply extending current technology. Atul Srivastava, an analyst at MarketsandMarkets, said that GaN wafers are also going to compete Si in several verticals across the industry due to its superior characteristics such as thermal conductivity. Ammonothermal, HVPE and Na-Flux LPE can be the best chosen manufacturing processes of GaN wafers with standard size of 2 inches.
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| * {{convert|1|in|mm|adj=on}}
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| * {{convert|2|in|mm|adj=on}}. Thickness 275 [[µm]].
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| * {{convert|3|in|mm|adj=on}}. Thickness 375 µm.
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| * {{convert|4|in|mm|adj=on}}. Thickness 525 µm.
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| * {{convert|5|in|mm|adj=on}} or 125 mm (4.9 inch). Thickness 625 µm.
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| * 150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.
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| * 200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.
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| * 300 mm (11.8 inch, usually referred to as "12 inch"). Thickness 775 µm.
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| * {{nowrap|450 mm}} (17.7 inch, usually referred to as "18 inch"). Thickness 925 µm (expected).<ref>[http://www.eetimes.com/electronics-news/4079657/Industry-agrees-on-first-450-mm-wafer-standard Industry Agrees on first 450-mm wafer standard - EETimes.com]</ref>
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| Wafers grown using materials other than silicon will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the [[mechanical strength]] of the material used; the wafer must be thick enough to support its own weight without cracking during handling.
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| A unit [[wafer fabrication]] step, such as an etch step or a lithography step, can be performed on more chips per wafer as roughly the square of the increase in wafer diameter, while the cost of the unit fabrication step goes up more slowly than the square of the wafer diameter. This is the cost basis for shifting to larger and larger wafer sizes. Conversion to 300 mm wafers from 200 mm wafers began in earnest in 2000, and reduced the price per die about 30-40%.<ref>[http://www.semiconductor.net/article/CA47551.html Semiconductor.net:Capability for {{nowrap|300 mm}}: Approaching Industry Goals]</ref>
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| However, this was not without significant problems for the industry.
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| The next step to 450 mm should accomplish similar productivity gains as the previous size increase.
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| However, machinery needed to handle and process larger wafers results in increased investment costs to build a single factory. There is considerable resistance to moving up to 450 mm despite the productivity enhancements, mainly because companies feel it would take too long to recoup their investment.<ref>[http://www.semiconductor.net/article/CA6445470.html?nid=3655 450 mm: A Promise Postponed]</ref> The difficult and costly 300 mm process only accounted for approximately 20% of worldwide capacity on a wafer area basis by the end of 2005.<ref>[http://www.semiconductor.net/article/CA6617173.html?nid=3660 A Simulation Study of the Cost and Economics of 450 mm Wafers]</ref> The step up to 300 mm required a major change from the past, with [[automatic factory|fully automated factories]] using 300 mm wafers versus barely automated factories for the 200 mm wafers. These major investments were undertaken in the [[economic downturn]] following the [[dot-com bubble]], resulting in huge resistance to upgrading to 450 mm by the original timeframe.
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| Other initial technical problems in the ramp up to 300 mm included vibrational effects, gravitational bending (sag), and problems with flatness. Among the new problems in the ramp up to 450 mm are that the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2-4 times longer to cool, and the process time will be double.<ref>[http://www.semiconductor.net/article/CA6617173.html?nid=3660 Semiconducter.net:Optimize Wafer Thickness for 450 mm]</ref> All told, the development of 450 mm wafers require significant engineering, time, and cost to overcome.
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| ====Analytical die count estimation====
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| In order to minimize the cost per [[die (electronics)|die]], manufacturers wish to maximize the number of dies that can be made from a single wafer; dies always have a square or rectangular shape due to the constraint of [[wafer dicing]]. In general, this is a [[computational complexity|computationally complex]] problem with no analytical solution, dependent on both the area of the dies as well as their [[aspect ratio]] (square or rectangular) and other considerations such as [[scribeline]] size and the space occupied alignment and test structures.
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| [[File:Wafermap_showing_fully_and_partially_patterned_dies.svg|thumb|Wafermap showing fully-patterned dies, and partially-patterned dies which don't fully lie within the wafer.]]Nevertheless, the number of gross die per wafer ('''DPW''') can be estimated starting with the [[first-order approximation]],
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| :<math>DPW = \left\lfloor\frac{\pi d^2}{4S}\right\rfloor</math>,
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| where <math>d</math> is the wafer diameter (typically in mm) and <math>S</math> the size of each die (mm<sup>2</sup>). This formula simply states that the number of dies which can fit on the wafer [[pigeonhole principle|cannot exceed]] the area of the wafer divided by the area of each individual die. It will always overestimate the true best-case gross DPW, since it includes the area of partially-patterned dies which do not fully lie on the wafer surface (see figure). These partially-patterned dies don't represent complete [[integrated circuit|IC]]s, so they cannot be sold as functional parts.
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| Refinements of this simple formula typically either add an edge correction, to account for partial dies on the edge, which in general will be more significant when the area of the die is large compared to the total area of the wafer. In the other limiting case (infinitesimally small dies or infinitely large wafers), the edge correction is negligible. The correction factor or correction term generally takes one of the forms cited by De Vries,<ref name="devries">{{cite journal|title=Investigation of gross die per wafer formulas|author1=Dirk K. de Vries|journal=IEEE Transactions on Semiconductor Manufacturing|issue=February 2005|pages=136-139|doi=10.1109/TSM.2004.836656}}</ref>
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| :<math>DPW = \frac{\displaystyle \pi d^2}{4S} - \frac{\displaystyle \pi d}{\sqrt{2S}}</math> (area ratio - circumference/(die diagonal length)) | |
| :or <math>DPW = \left(\frac{\displaystyle \pi d^2}{4S}\right) \exp(-2 \sqrt{S}/d)</math> (area ratio scaled by an exponential factor) | |
| :or <math>DPW = \frac{\displaystyle \pi d^2}{4S} \left(1 - \frac{\displaystyle 2\sqrt{S}}{d} \right)^2</math> (area ratio scaled by a polynomial factor)
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| Studies comparing these analytical formulas to [[brute-force]] computational results show that the formulas can be made more accurate, over practical ranges of die sizes and aspect ratios, by adjusting the coefficients of the corrections to values above or below unity, and by replacing the linear die dimension <math>\sqrt{S}</math> with <math>(H+W)/2</math> (average side length) in the case of dies with large aspect ratio:<ref name="devries"/>
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| :<math>DPW = \frac{\displaystyle \pi d^2}{4S} - 0.58^{*} \frac{\displaystyle \pi d}{\sqrt{S}}</math>
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| :or <math>DPW = \left(\frac{\displaystyle \pi d^2}{4S}\right) \exp(-2.32^{*} \sqrt{S}/d)</math>
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| :or <math>DPW = \frac{\displaystyle \pi d^2}{4S} \left(1 - \frac{\displaystyle 1.16^{*} \sqrt{S}}{d} \right)^2</math>
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| Note, that the gross DPW does ''not'' take into account yield loss due to defect or parametric issues.
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| ===Crystalline orientation===
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| [[Image:Silicon-unit-cell-3D-balls.png|thumb|Diamond Cubic Crystal Structure, Silicon unit cell]] | |
| [[Image:Wafer flats convention v2.svg|thumb|Flats can be used to denote [[doping (semiconductors)|doping]] and [[crystallography|crystallographic]] orientation. Red represents material that has been removed.]]
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| Wafers are grown from crystal having a regular [[crystal structure]], with silicon having a [[diamond cubic]] structure with a lattice spacing of 5.430710 Å (0.5430710 nm).<ref name=HandbookSi>{{cite book |last=O'Mara |first=William C. |year=1990|title=Handbook of Semiconductor Silicon Technology |pages =349–352 |publisher=William Andrew Inc. |isbn=0-8155-1237-6 |url=http://books.google.com/books?id=COcVgAtqeKkC&pg=PA351&dq=Czochralski+Silicon+Crystal+Face+Cubic |accessdate=2008-02-24}}</ref> When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the [[Miller index]] with (100) or (111) faces being the most common for silicon.<ref name=HandbookSi/>
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| Orientation is important since many of a single crystal's structural and electronic properties are highly [[anisotropic]]. [[Ion implantation]] depths depend on the wafer's crystal orientation, since each direction offers distinct [[Ion_implantation#Ion_channelling|paths]] for transport.<ref>{{cite book |last=Nishi |first=Yoshio |year=2000 |title=Handbook of Semiconductor Manufacturing Technology |pages=108–109 |publisher=CRC Press |isbn=0-8247-8783-8 |url=http://books.google.com/books?id=Qi98H-iTgLEC&pg=PA70&dq=wafer+flat+and+notch#PPA71,M1 |accessdate=2008-02-25}}</ref>
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| Wafer [[cleavage (crystal)|cleavage]] typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("[[Die (integrated circuit)|die]]s") so that the billions of individual [[Electronic component|circuit elements]] on an average wafer can be separated into many individual circuits.
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| ===Wafer flats and crystallographic orientation notches===
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| Wafers under 200 mm diameter have ''flats'' cut into one or more sides indicating the [[crystallography|crystallographic]] planes of the wafer (usually a {110} face). In earlier-generation wafers a pair of flats at different angles additionally conveyed the doping type (see illustration for conventions). Wafers of 200 mm diameter and above use a single small notch to convey wafer orientation, with no visual indication of doping type.<ref>{{Cite web |title=Wafer Flats |url=http://www.tf.uni-kiel.de/matwis/amat/elmat_en/kap_5/illustr/i5_2_4.html |accessdate=2008-02-23}}</ref>
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| ===Impurity doping===
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| Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity [[Doping (semiconductors)|doping]] concentration between 10<sup>13</sup> and 10<sup>16</sup> atoms per cm<sup>3</sup> of [[boron]], [[phosphorus]], [[arsenic]], or [[antimony]] which is added to the melt and defines the wafer as either bulk n-type or p-type.<ref>{{cite book |last=Widmann |first=Dietrich |year=2000 |title=Technology of Integrated Circuits |pages=39 |publisher=Springer |isbn=3-540-66199-9 |url=http://books.google.com/books?id=uYNn1N6YSwQC&pg=PA39&dq=Czochralski+Doping+Silicon |accessdate=2008-02-24}}</ref> However, compared with single-crystal silicon's atomic density of 5×10<sup>22</sup> atoms per cm<sup>3</sup>, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some [[interstitial defect|interstitial]] oxygen concentration. Carbon and metallic contamination are kept to a minimum.<ref>{{cite book |title=Microelectronic Materials and Processes |last=Levy |first=Roland Albert |year=1989 |pages=6–7, 13 |isbn=0-7923-0154-4 |url=http://books.google.com/books?id=wZPRPU6ne7UC&pg=PA248#PPA1,M1 |accessdate=2008-02-23}}</ref> [[Transition metal]]s, in particular, must be kept below parts per billion concentrations for electronic applications.<ref>{{cite book |title=The Materials Science of Semiconductors|last=Rockett |first=Angus |year=2008 |pages=13 |isbn=978-0-387-25653-5}}</ref>
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| ==Compound semiconductors==
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| While silicon is the prevalent material for wafers used in the electronics industry, other [[compound semiconductor|compound]] [[List of semiconductor materials|III-V]] or [[List of semiconductor materials|II-VI]] materials have also been employed. [[Gallium arsenide]] (GaAs), a [[III-V semiconductor]] produced via the [[Czochralski process]], is also a common wafer material.<ref name=Grover>{{cite book |title=Microelectronic Materials |last=Grovenor |first= C. |year= 1989 |isbn=0-85274-270-3 |publisher=CRC Press |pages=113–123 |url=http://books.google.com/books?id=Ecl_mnz1xcUC&pg=PA122&dq=GaAs+Wafer+Manufacture#PPA113,M1 |accessdate=2008-02-25}}</ref>
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| ==See also==
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| *[[Monocrystalline silicon]]
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| *[[Epilayer]]
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| *[[Epitaxy]]
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| *[[p-n junction|Junction]]
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| *[[Layer (electronics)]]
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| *[[Low-cost solar cell]]
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| *[[Rapid thermal processing]]
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| *[[Refining]]
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| *[[Screen printing]]
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| *[[SEMI font]]
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| *[[Silicon on insulator]] (SOI) wafers
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| *[[Solar panel]]
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| *[[RCA clean]]
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| *[[Melting]]
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| *[[Klaiber's law]]
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| *[[Wafer bonding]]
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| ==References==
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| {{Reflist|30em}}
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| ==External links==
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| {{Commons category|Wafers}}
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| * [http://www.ee.byu.edu/cleanroom/everything_wafers.phtml Everything Wafers] - A guide to semiconductor substrates type, property, cleaving, etching, and fabrication.
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| * [http://mrhackerott.org/semiconductor-informatics/informatics/toolz/DPWCalculator/Input.html Die per wafer calculator] by Michael Hackerott - includes many options for die size, spacing, and other layout considerations
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| {{DEFAULTSORT:Wafer (Electronics)}}
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| [[Category:Semiconductor device fabrication]]
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