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| {{Infobox CPU architecture
| | == then added with == |
| | name = MIPS
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| | designer = [[MIPS Technologies|MIPS Technologies, Inc.]]
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| | bits = [[64-bit]] (32→64)
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| | introduced = 1981
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| | version =
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| | design = [[Reduced instruction set computer|RISC]]
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| | type = Register-Register
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| | encoding = Fixed
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| | branching = Condition register
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| | endianness = [[Bi-endian|Bi]]
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| | extensions = [[MDMX]], [[MIPS-3D]]
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| | open =
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| | gpr = 31 (R0=0)
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| | fpr = 32 (paired DP for 32-bit)
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| }}
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| '''MIPS''' (originally an acronym for '''Microprocessor without Interlocked Pipeline Stages''') is a [[RISC|reduced instruction set computer]] (RISC) [[instruction set architecture]] (ISA) developed by [[MIPS Technologies]] (formerly MIPS Computer Systems, Inc.). The early MIPS architectures were 32-bit, with 64-bit versions added later. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations).<ref>{{cite web|url= http://www.imgtec.com/mips/mips32-architecture.asp|title= MIPS32 Architecture|publisher=[[Imagination Technologies]]|accessdate=4 Jan 2014}}</ref><ref>{{cite web|url= http://www.imgtec.com/mips/mips64-architecture.asp|title= MIPS64 Architecture|publisher=[[Imagination Technologies]]|accessdate=4 Jan 2014}}</ref> MIPS32 and MIPS64 define a control register set as well as the instruction set.
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| Several optional extensions are also available, including [[MIPS-3D]] which is a simple set of floating-point [[SIMD]] instructions dedicated to common 3D tasks,<ref>{{cite web|url= http://www.imgtec.com/mips/mips-3d-ase.asp|title= MIPS-3D ASE|publisher=[[Imagination Technologies]]|accessdate=4 Jan 2014}}</ref> [[MDMX]] (MaDMaX) which is a more extensive integer [[SIMD]] instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room,<ref>{{cite web|url= http://www.imgtec.com/mips/mips-16e-ase.asp|title= MIPS16e|publisher=[[Imagination Technologies]]|accessdate=4 Jan 2014}}</ref> and MIPS MT, which adds [[Multithreading (computer architecture)|multithreading]] capability.<ref>{{cite web|url= http://www.imgtec.com/mips/mips-multithreading.asp|title= MIPS Multithreading|publisher=[[Imagination Technologies]]|accessdate=4 Jan 2014}}</ref>
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| | 相关的主题文章： |
| | <ul> |
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| | <li>[http://www.mengweixs.com/plus/feedback.php?aid=69 http://www.mengweixs.com/plus/feedback.php?aid=69]</li> |
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| [[Computer architecture]] courses in universities and technical schools often study the MIPS architecture.<ref>{{cite web|url= http://www.cs.ucdavis.edu/~peisert/teaching/ecs142-sp09/rt.html|title=ECS 142 (Compilers) References & Tools page|author=University of California, Davis|accessdate=28 May 2009}}</ref> The architecture greatly influenced later RISC architectures such as [[DEC Alpha|Alpha]].
| | == actually buy a house == |
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| MIPS implementations are primarily used in [[embedded system]]s such as [[Windows CE]] devices, [[Router (computing)|router]]s, [[residential gateway]]s, and [[video game console]]s such as the [[Sony]] [[PlayStation 2]] and [[PlayStation Portable]]. Until late 2006, they were also used in many of [[Silicon Graphics|SGI]]'s computer products. MIPS implementations were also used by [[Digital Equipment Corporation]], [[NEC]], [[Pyramid Technology]], [[Siemens Nixdorf]], [[Tandem Computers]] and others during the late 1980s and 1990s. In the mid to late 1990s, it was estimated that one in three RISC microprocessors produced was a MIPS implementation.<ref name="Victor P. Rubio, 2004">{{cite web|last=Rubio|first=Victor P|title=A FPGA Implementation of a MIPS RISC Processor for Computer Architecture Education|url=http://www.ece.nmsu.edu/~jecook/thesis/Victor_thesis.pdf|publisher=[[New Mexico State University]]|accessdate=22 December 2011}}</ref>
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| | | 相关的主题文章： |
| == Versions of the MIPS instruction set ==
| | <ul> |
| [[File:MIPS instruction set family.svg|thumb|A diagram demonstrating the relations of the MIPS I, MIPS II, MIPS III MIPS IV, MIPS32 and MIPS64 instruction sets between one another.]]
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| | | <li>[http://projectdelta.net/cgi-bin/guestbook/guestbook.cgi http://projectdelta.net/cgi-bin/guestbook/guestbook.cgi]</li> |
| Processors based upon the MIPS instruction set have been in production since 1988. Over time several enhancements of the instruction set were made. The different revisions which have been introduced are MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V. Each revision is a superset of its predecessors. When MIPS Technologies was spun out of [[Silicon Graphics]] again in 1998, they refocused on the embedded market. At that time, this superset property was found to be a problem, and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 instruction set.
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| | | <li>[http://852360.134218.20la.com.cn/forum.php?mod=viewthread&tid=278259 http://852360.134218.20la.com.cn/forum.php?mod=viewthread&tid=278259]</li> |
| === MIPS I ===
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| Introduced in 1985 with the [[R2000 (microprocessor)|R2000]].
| | <li>[http://www.xddfl.com/home.php?mod=space&uid=9077 http://www.xddfl.com/home.php?mod=space&uid=9077]</li> |
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| === MIPS II ===
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| Introduced in 1990 with the [[R6000]].
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| === MIPS III ===
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| Introduced in 1992 in the [[R4000]]. It adds 64-bit registers and integer instructions and a square root [[floating point]] instruction.
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| === MIPS IV ===
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| MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS. The first implementation of MIPS IV was the [[R8000]], which was introduced in 1994. MIPS IV added:
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| * Register + register [[Addressing modes|addressing]] for floating point loads and stores
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| * Single- and double-precision floating point fused-multiply adds and subtracts
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| * Conditional move instructions for both integer and floating-point
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| * Extra condition bits in the floating point control and status register, bringing the total to eight
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| === MIPS V ===
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| Announced on 21 October 1996 at the Microprocessor Forum 1996.<ref>{{cite web|url= http://infopad.eecs.berkeley.edu/CIC/otherpr/enhanced_mips.html|title=Silicon Graphics Introduces Enhanced MIPS Architecture to Lead the Interactive Digital Revolution|publisher=[[Silicon Graphics, Inc.]]|date=21 October 1996}}</ref> MIPS V was designed to improve the performance of 3D graphics applications. In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from SGI. MIPS V was complemented by the integer-only [[MDMX|MIPS Digital Media Extensions]] (MDMX) multimedia extensions, which were announced on the same date as MIPS V.<ref name="MPR:1996-11-18">[http://studies.ac.upc.edu/ETSETB/SEGPAR/microprocessors/mdmx%20(mpr).pdf Gwennap, Linley (18 November 1996). "Digital, MIPS Add Multimedia Extensions".] ''Microprocessor Report''. pp. 24–28.</ref>
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| MIPS V implementations were never introduced. In 1997, SGI announced the "H1" or "Beast" and the "H2" or "Capitan" microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in 1999. The "H1" and "H2" projects were later combined and were eventually canceled in 1998.
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| MIPS V added a new data type, the pair-single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data. It was the first instruction set to exploit floating-point SIMD with existing resources.<ref name="MPR:1996-11-18"/>
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| === MIPS32 ===
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| Introduced in 1999 based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V.
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| ==== MIPS32 release 1 ====
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| ==== MIPS32 release 2 ====
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| ==== MIPS32 release 3 ====
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| ==== MIPS32 release 4 ====
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| The R4 designation was skipped due to the disastrous Halt and Catch Fire bug of 2003.
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| ==== MIPS32 release 5 ====
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| Announced on December 6, 2012.<ref>http://www.mips.com/news-events/newsroom/newsindex/index.dot?id=79069 Announcing Release5</ref>
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| === MIPS64 ===
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| Introduced in 1999 based on MIPS V. [[Nippon Electric Corporation|NEC]], [[Toshiba]] and [[SiByte]] (later acquired by [[Broadcom]]) each obtained licenses for the MIPS64 instruction set as soon as it was announced. [[Philips]], [[LSI Corporation|LSI Logic]], [[Integrated Device Technology|IDT]], [[RMI Corporation|Raza Microelectronics, Inc.]], [[Cavium]], [[Loongson|Loongson Technology]] and [[Ingenic Semiconductor]] have since joined them.
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| == Application-specific extensions ==
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| === MCU ===
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| Enhancements for microcontroller applications.
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| === SmartMIPS ===
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| Extends the MIPS32 Architectures with a set of security enhancements.
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| === MDMX ===
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| {{main|MDMX}}
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| === MIPS-3D ===
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| {{main|MIPS-3D}}
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| === MIPS16e ===
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| Contains 16-bit compressed code instructions. The core can execute both 16- and 32-bit instructions intermixed in the same program, and is compatible with both the MIPS32 and MIPS64 Architectures.
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| === microMIPS ===
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| microMIPS32 and microMIPS64 are high performance code compression technologies that combine optimized 16- and 32-bit instructions in single, unified Instruction Set. As a complete ISA, microMIPS can operate standalone or in co-existence with the legacy-compatible MIPS32 instruction decoder, allowing programs to intermix 16- and 32-bit code without having to switch modes. microMIPS32 has 32x32b registers; 32 bits Virtual Address, up to 36 bits Physical Address (same as MIPS32). microMIPS64 has 32x64b registers; 64 bits Virtual Address, up to 59 bits Physical Address, adds 64- bit variables (same as MIPS64)
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| == Microarchitectures based on the MIPS instruction set ==
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| {{main|List of MIPS microprocessor cores}}
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| [[File:MIPS Architecture (Pipelined).svg|thumb|right|300px|Pipelined MIPS, showing the five stages (instruction fetch, instruction decode, execute, memory access and write back).]]
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| The first commercial MIPS model, the '''[[R2000 (microprocessor)|R2000]]''', was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the register file; these result-retrieving instructions were interlocked.
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| The R2000 could be booted either [[big-endian]] or [[little-endian]]. It had thirty-one 32-bit general purpose registers, but no [[Condition Code Register|condition code register]] (the designers considered it a potential bottleneck), a feature it shares with the [[AMD 29000]] and the [[DEC Alpha|Alpha]]. Unlike other registers, the [[program counter]] is not directly accessible.
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| The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional '''R2010''' [[floating point unit|FPU]], which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.
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| MIPSel refers to a MIPS architecture using a little endian byte order. Since almost all MIPS microprocessors have the capability of operating with either little endian or big endian byte order, the term is used only for processors where little endian byte order has been pre-determined.
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| The '''[[R3000]]''' succeeded the R2000 in 1988, adding 32 kB (soon increased to 64 kB) caches for instructions and data, along with [[cache coherency]] support for multiprocessor use. While there were flaws in the R3000s multiprocessor support, it still managed to be a part of several successful multiprocessor designs. The R3000 also included a built-in [[Memory management unit|MMU]], a common feature on CPUs of the era. The R3000, like the R2000, could be paired with a '''R3010''' FPU. The R3000 was the first successful MIPS design in the marketplace, and eventually over one million were made. A speed-bumped version of the R3000 running up to 40 MHz, the '''R3000A''' delivered a performance of 32 [[Million instructions per second|VUPs (VAX Unit of Performance)]]. The MIPS R3000A-compatible '''R3051''' running at 33.8688 MHz was the processor used in the [[Sony]] [[PlayStation]]. Third-party designs include Performance Semiconductor's '''R3400''' and IDT's '''R3500''', both of them were R3000As with an integrated R3010 FPU. [[Toshiba]]'s '''R3900''' was a virtually first [[System-on-a-chip|SoC]] for the early [[handheld PC]]s that ran [[Windows CE]]. A [[radiation-hardened]] variant for space applications, the [[Mongoose-V]], is a R3000 with an integrated R3010 FPU.
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| The '''[[R4000]]''' series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip microprocessor, and operated at a radically high internal clock speed (it was introduced at 100 MHz). However, in order to achieve the clock speed the caches were reduced to 8 kB each and they took three cycles to access. The high operating frequencies were achieved through the technique of [[deep pipelining]] (called super-pipelining at the time). The improved '''R4400''' followed in 1993. It had larger 16 kB primary caches, largely bug-free 64-bit operation, and support for a larger L2 cache.
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| MIPS, now a division of SGI called MTI, designed the low-cost '''[[R4200]]''', the basis for the even cheaper '''[[R4300i]]'''. A derivative of this microprocessor, the [[NEC Corporation|NEC]] VR4300, was used in the [[Nintendo 64]] game console.<ref>[http://www.nec.co.jp/press/en/9801/2002.html NEC Offers Two High Cost Performance 64-bit RISC Microprocessors]</ref>
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| [[Image:IDT R4700 diephoto2.jpg|thumb|Bottom-side view of package of R4700 Orion with the exposed silicon chip, fabricated by [[Integrated Device Technology|IDT]], designed by [[Quantum Effect Devices]].]]
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| [[Image:KL IDT R4700 MIPS Microprocessor.jpg|thumb|Top-side view of package for R4700 Orion]]
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| [[Quantum Effect Devices]] (QED), a separate company started by former MIPS employees, designed the '''R4600''' ''Orion'', the '''R4700''' ''Orion'', the '''R4650''' and the '''R5000'''. Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the [[SGI Indy]] workstation as well as the first MIPS based Cisco routers, such as the 36x0 and 7x00-series routers. The R4650 was used in the original [[WebTV]] [[set-top box]]es (now Microsoft TV). The R5000 FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement. QED later designed the '''RM7000''' and '''RM9000''' family of devices for embedded markets like networking and laser printers. QED was acquired by the semiconductor manufacturer [[PMC-Sierra]] in August 2000, the latter company continuing to invest in the MIPS architecture. The '''RM7000''' included an on-board 256 kB level 2 cache and a controller for optional level three cache. The '''RM9xx0''' were a family of [[System-on-a-chip|SOC]] devices which included [[Northbridge (computing)|northbridge]] peripherals such as [[memory controller]], [[Peripheral Component Interconnect|PCI]] controller, [[gigabit ethernet]] controller and fast IO such as a [[hypertransport]] port.
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| The '''[[R8000]]''' (1994) was the first [[superscalar]] MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 kB instruction and 16 kB data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's [[SGI Challenge|POWER Challenge]] servers in the mid-1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users, and the R8000 was in the marketplace for only a year and remains fairly rare.
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| In 1995, the '''[[R10000]]''' was released. This processor was a single-chip design, ran at a faster clock speed than the R8000, and had larger 32 kB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.
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| Later designs have all been based upon R10000 core. The '''[[R10000#R12000|R12000]]''' used a 0.25 micrometre process to shrink the chip and achieve higher clock rates. The revised '''[[R10000#R14000|R14000]]''' allowed higher clock rates with additional support for [[DDR SDRAM|DDR]] [[Static random access memory|SRAM]] in the off-chip [[CPU cache|cache]]. Later iterations are named the '''[[R10000#R16000|R16000]]''' and the '''R16000A''' and feature increased clock speed and smaller die manufacturing compared with before.
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| Other members of the MIPS family include the '''[[R6000]]''', an [[Emitter-coupled logic|ECL]] implementation produced by [[Bipolar Integrated Technology]]. The R6000 introduced the MIPS II instruction set. Its [[Translation Lookaside Buffer|TLB]] and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in [[Control Data]] machines, it quickly disappeared from the mainstream market.
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| ==History==
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| ===RISC pioneer===
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| In 1981, a team led by [[John L. Hennessy]] at [[Stanford University]] started work on what would become the first MIPS processor. The basic concept was to increase performance through the use of deep [[instruction pipeline]]s. Pipelining as a basic technique was well known before (see [[IBM 801]] for instance), but not developed into its full potential. CPUs are built up from a number of dedicated sub-units such as instruction decoders, ALUs (integer arithmetics and logic), [[load/store architecture|load/store]] units (handling memory), and so on. In a traditional non-optimized design, a particular instruction in a program sequence must be (almost) completed before the next can be issued for execution; in a pipelined architecture, successive instructions can instead overlap in execution. For instance, at the same time a math instruction is fed into the floating point unit, the load/store unit can fetch the next instruction.
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| One major barrier to pipelining was that some instructions, like division, take longer to complete and the CPU therefore has to wait before passing the next instruction into the pipeline. One solution to this problem is to use a series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream. Hennessy's team viewed these interlocks as a major performance barrier since they had to communicate to all the modules in the CPU which takes time, and appeared to limit the [[clock speed]]. A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.
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| Although this design eliminated a number of useful instructions such as multiply and divide it was felt that the overall performance of the system would be dramatically improved because the chips could run at much higher clock rates. This ramping of the speed would be difficult with interlocking involved, as the time needed to set up locks is as much a function of die size as clock rate. The elimination of these instructions became a contentious point.
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| The other difference between the MIPS design and the competing [[Berkeley RISC]] involved the handling of [[subroutine]] calls. RISC used a technique called [[register window]]s to improve performance of these very common tasks, but this limited the maximum depth of multi-level calls. Each subroutine call required its own set of registers, which in turn required more real estate on the CPU and more complexity in its design. Hennessy felt that a careful compiler could find free registers without resorting to a hardware implementation, and that simply increasing the number of registers would not only make this simple, but increase the performance of all tasks.
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| In other ways the MIPS design was very much a typical RISC design. To save bits in the instruction word, RISC designs reduce the number of instructions to encode. The MIPS design uses 6 bits of the 32-bit word for the basic opcode;<ref>[[Morgan Kaufmann Publishers]], ''Computer Organization and Design'', [[David Patterson (scientist)|David A. Patterson]] & [[John L. Hennessy]], Edition 3, ISBN 1-55860-604-1, page 63</ref> the rest may contain a single 26-bit jump address or it may have up to four 5-bit fields specifying up to three registers plus a shift value combined with another 6-bits of opcode; another format, among several, specifies two registers combined with a 16-bit immediate value, etc. This allowed this CPU to load up the instruction and the data it needed in a single cycle, whereas an (older) non-RISC design, such as the [[MOS Technology 6502]] for instance, required separate cycles to load the opcode and the data. This was one of the major performance improvements that RISC offered. However, modern non-RISC designs achieve this speed by other means (such as queues in the CPU).
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| ===First hardware===
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| In 1984 Hennessy was convinced of the future commercial potential of the design, and left Stanford to form MIPS Computer Systems. They released their first design, the '''[[R2000 (microprocessor)|R2000]]''', in 1985, improving the design as the '''[[R3000]]''' in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in [[Silicon Graphics|SGI]]'s series of [[workstation]]s and later [[Digital Equipment Corporation]] DECstation workstations and servers. The SGI commercial designs deviated from the Stanford academic research by implementing most of the interlocks in hardware, supplying full multiply and divide instructions (among others). The designs were guided, in part, by software architect [[Earl Killian]] who designed the MIPS III 64-bit instruction-set extension, and led the work on the R4000 microarchitecture.<ref name=twsNovZ23>{{cite news
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| |title= Earl Killian
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| |publisher= ''Paravirtual''
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| |date= 26 November 2010
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| |url= http://www.paravirtual.com/content/company/advisory_board.htm
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| |accessdate=26 November 2010
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| }}</ref><ref name=twsNovZ14>{{cite news
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| |title= S-1 Supercomputer Alumni: Earl Killian
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| |publisher= ''Clemson University''
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| |quote= Earl Killian's early work w... As MIPS's Director of Architecture, he designed the MIPS III 64-bit instruction-set extension, and led the work on the R4000 microarchitecture. He was a cofounder of QED, which created the R4600 and R5000 MIPS processors. Most recently he was chief architect at Tensilica working on configurable/extensible processors.
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| |date= 28 June 2005
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| |url= http://www.cs.clemson.edu/~mark/s1_alumni.html
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| |accessdate=26 November 2010
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| }}</ref>
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| In 1991 MIPS released the first 64-bit microprocessor, the '''[[R4000]]'''. The R4000 has an advanced [[Translation lookaside buffer|TLB]] where the entry contains not just virtual address but also the virtual address space id. Such buffer eliminates the major performance problems from [[microkernel]]s<ref>Jochen Liedtke(1995). On micro kernel construction. 15th Symposium on Operating Systems Principles, Copper Mountain Resort, Colorado.</ref> that are slow on competing architectures (Pentium, PowerPC, Alpha) because of the need to flush the TLB on the frequent context switches. However, MIPS had financial difficulties while bringing it to market. The design was so important to SGI, at the time one of MIPS' few major customers, that SGI bought the company outright in 1992 in order to guarantee the design would not be lost. As a subsidiary of SGI, the company became known as [[MIPS Technologies]].
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| ===Licensable architecture===
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| In the early 1990s MIPS started licensing their designs to third-party vendors. This proved fairly successful due to the simplicity of the core, which allowed it to be used in a number of applications that would have formerly used much less capable [[Complex instruction set computer|CISC]] designs of similar [[gate count]] and price—the two are strongly related; the price of a CPU is generally related to the number of gates and the number of external pins. [[Sun Microsystems]] attempted to enjoy similar success by licensing their [[SPARC]] core but was not nearly as successful. By the late 1990s MIPS was a powerhouse in the [[embedded processor]] field. According to MIPS Technologies Inc., there was an exponential growth, with 48-million MIPS-based CPU shipments and 49% of total RISC CPU market share in 1997.<ref name="MIPS Brochure">{{cite web | url=http://www.warthman.com/images/MIPS%20Brochure%20Optimized.pdf | title=MIPS Brochure | publisher=MIPS Technologies Inc. | accessdate=March 2, 2013}}</ref> MIPS was so successful that SGI spun off MIPS Technologies in 1998. Fully half of MIPS's income today comes from licensing their designs, while much of the rest comes from contract design work on cores that will then be produced by third parties.
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| In 1999 MIPS formalized their licensing system around two basic designs, the 32-bit '''MIPS32''' (based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V) and the 64-bit '''MIPS64''' (based on MIPS V). [[Nippon Electric Corporation|NEC]], [[Toshiba]] and [[SiByte]] (later acquired by [[Broadcom]]) each obtained licenses for the MIPS64 as soon as it was announced. [[Philips]], [[LSI Corporation|LSI Logic]] and [[Integrated Device Technology|IDT]] have since joined them. Today, the MIPS cores are one of the most-used "heavyweight"{{Clarify|date=June 2009}} cores in the marketplace for computer-like devices ([[hand-held computer]]s, set-top boxes, etc.).
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| Since the MIPS architecture is licensable, it has attracted several processor [[Startup company|start-up]] companies over the years. One of the first start-ups to design MIPS processors was [[Quantum Effect Devices]] (see next section). The MIPS design team that designed the '''[[R4300i]]''' started the company [[SandCraft]], which designed the '''R5432''' for NEC and later produced the '''SR71000''', one of the first [[out-of-order execution]] processors for the embedded market. The original [[Digital Equipment Corporation|DEC]] [[StrongARM]] team eventually split into two MIPS-based start-ups: SiByte which produced the '''SB-1250''', one of the first high-performance MIPS-based [[system-on-a-chip|systems-on-a-chip]] (SOC); while [[Alchemy Semiconductor]] (later acquired by [[AMD]]) produced the '''Au-1000''' [[system-on-a-chip|SoC]] for low-power applications. [[Lexra]] used a MIPS-''like'' architecture and added DSP extensions for the audio chip market and [[Multithreading (computer architecture)|multithreading]] support for the networking market. Due to Lexra not licensing the architecture, two lawsuits were started between the two companies. The first was quickly resolved when Lexra promised not to advertise their processors as MIPS-compatible. The second (about MIPS patent 4814976 for handling unaligned memory access) was protracted, hurt both companies' business, and culminated in MIPS Technologies giving Lexra a free license and a large cash payment.
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| Two companies have emerged that specialize in building [[Multi-core (computing)|multi-core]] devices using the MIPS architecture. [[RMI Corporation|Raza Microelectronics, Inc.]] purchased the product line from failing SandCraft and later produced devices that contained eight cores that were targeted at the telecommunications and networking markets. [[Cavium]], originally a security processor vendor also produced devices with eight CPU cores, and later up to 32 cores, for the same markets. Both of these companies designed their cores in-house, just licensing the architecture instead of purchasing cores from MIPS.
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| ===The desktop===
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| {{further2|[[Advanced Computing Environment]]}}
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| Among the manufacturers which have made computer [[workstation]] systems using MIPS processors are [[Silicon Graphics|SGI]], [[MIPS Computer Systems, Inc.]], [[Whitechapel Workstations]], [[Olivetti]], [[Siemens Nixdorf Informationssysteme|Siemens-Nixdorf]], [[Acer (company)|Acer]], [[Digital Equipment Corporation]], [[NEC Corporation|NEC]], and [[DeskStation]].
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| [[Operating system]]s ported to the architecture include SGI's [[IRIX]], [[Microsoft]]'s [[Windows NT]] (until v4.0), [[Windows CE]], [[Linux]], [[BSD]], [[Unix|UNIX]] [[System V]], [[SINIX]], [[QNX]], and MIPS Computer Systems' own [[RISC/os]].
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| There was speculation in the early 1990s that MIPS and other powerful [[RISC]] processors would overtake the Intel [[IA32]] architecture. This was encouraged by the support of the first two versions of [[Microsoft]]'s [[Windows NT]] for [[DEC Alpha|Alpha]], MIPS and [[PowerPC]]—and to a lesser extent the [[Clipper architecture]] and [[SPARC]]. However, as Intel quickly released faster versions of their [[Pentium (brand)|Pentium]] class CPUs, Microsoft [[Windows NT]] v4.0 dropped support for anything but IA32 and Alpha. With [[Silicon_Graphics|SGI]]'s decision to transition to the [[Itanium]] and [[IA32]] architectures in 2007 (following a 2006 Chapter 11 bankruptcy<ref>{{cite web url=http://online.wsj.com/article/SB114708367971646497.html |title=Silicon Graphics Seeks Chapter 11 As Sales Decline |work=Wall Street Journal |date=05/06/2006. (subscription required)}}</ref>) and 2009 acquisition by [[Silicon_Graphics_International|Rackable Systems, Inc.]], support ended for the MIPS/IRIX consumer market in December, 2013 as originally scheduled. However, a support team still exists for special circumstances and refurbished systems that are still available on a limited basis.<ref>{{cite web |url=http://www.sgi.com/services/support/irix_mips.html |title=End of General Availability for MIPS® IRIX® Products |work= |date=2013 }}</ref>
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| ===Embedded markets===
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| [[File:Ingenic JZ4730.JPG|thumb|168px|The [[Ingenic]] JZ4730 is an example for a MIPS based [[System on Chip|SoC]].]]
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| Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in [[computer network]]ing, [[telecommunications]], [[video arcade game]]s, [[video game console]]s, [[computer printer]]s, digital [[set-top box]]es, [[digital television]]s, [[DSL modem|DSL]] and [[cable modem]]s, and [[personal digital assistant]]s.
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| The low power-consumption and heat characteristics of embedded MIPS implementations, the wide availability of embedded development tools, and knowledge about the architecture means use of MIPS microprocessors in embedded roles is likely to remain common.
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| === Synthesizeable cores for embedded markets ===
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| In recent years{{when|date=May 2013}} most of the technology used in the various MIPS generations has been offered as [[Semiconductor intellectual property core|IP-cores]] (building-blocks) for [[embedded processor]] designs. Both [[32-bit]] and [[64-bit]] basic cores are offered, known as the '''4K''' and '''5K'''. These cores can be mixed with add-in units such as [[Floating-point unit|FPU]]s, [[SIMD]] systems, various input/output devices, etc.
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| MIPS cores have been commercially successful, now being used in many consumer and industrial applications. MIPS cores can be found in newer [[Cisco]], [[Linksys]] and [[Mikrotik|Mikrotik's routerboard]] routers, [[cable modem]]s and [[Asymmetric Digital Subscriber Line|ADSL]] modems, [[smartcard]]s, [[laser printer]] engines, [[set-top box]]es, [[robot]]s, handheld computers, [[Nintendo 64]], Sony [[PlayStation 2]] and Sony [[PlayStation Portable]]. In cellphone/PDA applications, MIPS has been largely unable to displace the incumbent, competing [[ARM architecture]].
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| MIPS architecture processors include: IDT RC32438; ATI/AMD [[Xilleon]]; Alchemy Au1000, 1100, 1200; Broadcom Sentry5; [[RMI Corporation|RMI]] XLR7xx, [[Cavium Networks|Cavium]] Octeon CN30xx, CN31xx, CN36xx, CN38xx and CN5xxx; [[Infineon Technologies]] EasyPort, Amazon, Danube, ADM5120, WildPass, INCA-IP, INCA-IP2; [[Microchip Technology]] PIC32; [[NEC]] EMMA and EMMA2, NEC VR4181A, VR4121, VR4122, VR4181A, VR4300, VR5432, VR5500; [[Oak Technologies]] Generation; [[PMC-Sierra]] RM11200; [[QuickLogic]] QuickMIPS ESP; Toshiba ''Donau'', [[Toshiba]] TMPR492x, TX4925, TX9956, TX7901.
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| === MIPS-based supercomputers ===
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| One of the more interesting applications of the MIPS architecture is its use in massive processor count supercomputers. [[Silicon Graphics]] (SGI) refocused its business from desktop graphics workstations to the [[high-performance computing]] market in the early 1990s. The success of the company's first foray into server systems, the [[SGI Challenge|Challenge]] series based on the R4400 and [[R8000]], and later [[R10000]], motivated SGI to create a vastly more powerful system. The introduction of the integrated R10000 allowed SGI to produce a system, the [[Origin 2000]], eventually scalable to 1024 CPUs using its [[NUMAlink]] cc-NUMA interconnect. The Origin 2000 begat the [[Origin 3000]] series which topped out with the same 1024 maximum CPU count but using the R14000 and R16000 chips up to 700 MHz. Its MIPS based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's IA-64 architecture.
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| A high-performance computing startup called [[SiCortex]] introduced a massively parallel MIPS based supercomputer in 2007. The machines are based on the MIPS64 architecture and a high performance interconnect using a [[Kautz graph]] topology. The system is very power efficient and computationally powerful.{{citation needed|date=May 2013}} The most innovative aspect of the system was its multicore processing node which integrates six MIPS64 cores, a [[crossbar switch]] [[memory controller]], interconnect [[Direct memory access|DMA]] engine, [[Gigabit Ethernet]] and [[PCI Express]] controllers all on a single chip which consumes only 10 watts of power, yet has a peak floating point performance of 6 [[FLOPS|gigaFLOPS]]. The most powerful configuration, the SC5832, is a single cabinet supercomputer consisting of 972 such node chips for a total of 5832 MIPS64 processor cores and 8.2 teraFLOPS of peak performance.
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| === Loongson ===
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| {{Main|Loongson}}
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| [[File:Loongson 2F.jpg|thumb|The [[Loongson]] 2F MIPS64 [[CPU]], part of [[China]]'s [[863 Program]]]]
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| [[Loongson]] is a MIPS-compatible family of microprocessors designed by the [[Chinese Academy of Sciences]]. The internal microarchitecture of Loongson microprocessors was designed independently by the Chinese, and early implementations of the family lacked four instructions patented by MIPS Technologies.<ref>[http://www.mdronline.com/mpr/h/2006/0626/202602.html China's Microprocessor Dilemma]</ref> In June 2009, ICT licenced the MIPS32 and MIPS64 architectures directly from MIPS Technologies.<ref>[http://www.mips.com/news-events/newsroom/release-archive-2009/6_15_09.dot China’s Institute of Computing Technology Licenses Industry-Standard MIPS Architectures]</ref>
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| Starting from 2006, a number of companies released Loongson-based computers, including [[nettop]]s and [[netbook]]s designed for low-power use.<ref>{{cite web|url=http://www.linuxfordevices.com/c/a/News/Chinese-150-Linux-miniPC-races-OLPC-to-market/|title=LinuxDevices article about the Municator|archiveurl=http://archive.is/8x37|archivedate=2012-12-16}}</ref><ref>{{cite web | url=http://www.linuxdevices.com/news/NS2928309621.html | title=''Yeelong'' Specs | publisher=LinuxDevices | date=22 October 2008|archiveurl=http://archive.is/T5He|archivedate=2012-12-10}}</ref>
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| ==== Dawning 6000 ====
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| {{Main|Dawning Information Industry#Dawning 6000}}
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| The high-performance Dawning 6000, which has a projected speed of over one quadrillion operations per second, will incorporate the [[Loongson]] processor as its core. Dawning 6000 is currently jointly developed by the Institute of Computing Technology under the Chinese Academy of Sciences and the Dawning Information Industry Company. Li Guojie, chairman of Dawning Information Industry Company and director and academician of the Institute of Computing Technology, said research and development of the Dawning 6000 is expected to be completed in two years. By then, Chinese-made high-performance computers will be expected to achieve two major breakthroughs: first, the adoption of domestic-made central processing units (CPUs); second, the existing cluster-based system structure of high-performance computers will be changed once the computing speed reaches one [[quadrillion]] operations per second.
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| ==MIPS I instruction formats==
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| Instructions are divided into three types: R, I and J. Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.<ref name="uidaho">[http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html MIPS R3000 Instruction Set Summary]</ref><ref>[http://www.xs4all.nl/~vhouten/mipsel/r3000-isa.html MIPS Instruction Reference]</ref>
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| The following are the three formats used for the core instruction set:
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| {| class="wikitable"
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| |-
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| ! Type || colspan=6| -31- format (bits) -0-
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| |- align=center
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| | '''R''' || opcode (6) || rs (5) || rt (5) || rd (5) || shamt (5) || funct (6)
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| |- align=center
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| | '''I''' || opcode (6) || rs (5) || rt (5) ||colspan=3| immediate (16)
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| |- align=center
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| | '''J''' || opcode (6) ||colspan=5| address (26)
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| |}
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| ==MIPS assembly language==
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| These are assembly language instructions that have direct hardware implementation, as opposed to ''pseudoinstructions'' which are translated into multiple real instructions before being assembled.
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| * In the following, the register letters ''d'', ''t'', and ''s'' are placeholders for (register) numbers or register names.
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| * ''C'' denotes a constant (''immediate'').
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| * All the following instructions are native instructions.
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| * Opcodes and funct codes are in hexadecimal.
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| * The MIPS32 Instruction Set states that the word ''unsigned'' as part of Add and Subtract instructions, is a ''misnomer''. The difference between ''signed'' and ''unsigned'' versions of commands is not a sign extension (or lack thereof) of the operands, but controls whether a trap is executed on overflow ''(e.g. Add)'' or an overflow is ignored ''(Add unsigned)''. An immediate operand CONST to these instructions is always sign-extended.
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| ===Integer===
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| MIPS has 32 integer registers. Data must be in registers to perform arithmetic. Register $0 always holds 0 and register $1 is normally reserved for the assembler (for handling pseudo instructions and large constants).
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| The encoding shows which bits correspond to which parts of the instruction. A hyphen (-) is used to indicate [[don't cares]].
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| {| class=wikitable
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| |-
| |
| !Category !! Name !! Instruction syntax !! Meaning !!colspan=3| Format/opcode/funct !! Notes/Encoding
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| |-
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| |rowspan=10| Arithmetic
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| ||Add || add $d,$s,$t || $d = $s + $t || R || 0 || 20<sub>16</sub> || adds two registers, executes a trap on overflow<br><pre>000000ss sssttttt ddddd--- --100000</pre>
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| |-
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| | Add unsigned || addu $d,$s,$t || $d = $s + $t || R || 0 || 21<sub>16</sub> || as above but ignores an overflow<br><pre>000000ss sssttttt ddddd--- --100001</pre>
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| |-
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| | Subtract || sub $d,$s,$t || $d = $s - $t || R || 0 || 22<sub>16</sub> || subtracts two registers, executes a trap on overflow<br><pre>000000ss sssttttt ddddd--- --100010</pre>
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| |-
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| | Subtract unsigned || subu $d,$s,$t || $d = $s - $t || R || 0 || 23<sub>16</sub> || as above but ignores an overflow<br><pre>000000ss sssttttt ddddd000 00100011</pre>
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| |-
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| | Add immediate || addi $t,$s,C || $t = $s + C (signed) || I || 8<sub>16</sub> || - || Used to add sign-extended constants (and also to copy one register to another: addi $1, $2, 0), executes a trap on overflow<br><pre>001000ss sssttttt CCCCCCCC CCCCCCCC</pre>
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| |-
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| | Add immediate unsigned || addiu $t,$s,C || $t = $s + C (signed) || I || 9<sub>16</sub> || - || as above but ignores an overflow<br><pre>001001ss sssttttt CCCCCCCC CCCCCCCC</pre>
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| |-
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| | Multiply || mult $s,$t || LO = (($s * $t) << 32) >> 32;<br /> HI = ($s * $t) >> 32; || R || 0 || 18<sub>16</sub> || Multiplies two registers and puts the 64-bit result in two special memory spots - LO and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $s * $t . See mfhi and mflo for accessing LO and HI regs.
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| |-
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| | Multiply unsigned || multu $s,$t || LO = (($s * $t) << 32) >> 32;<br /> HI = ($s * $t) >> 32; || R || 0 || 19<sub>16</sub> || Multiplies two registers and puts the 64-bit result in two special memory spots - LO and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $s * $t . See mfhi and mflo for accessing LO and HI regs.
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| |-
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| | Divide || div $s, $t || LO = $s / $t HI = $s % $t || R || 0 || 1A<sub>16</sub> || Divides two registers and puts the 32-bit integer result in LO and the remainder in HI.<ref name="uidaho"/>
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| |-
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| | Divide unsigned || divu $s, $t || LO = $s / $t HI = $s % $t || R || 0 || 1B<sub>16</sub> || Divides two registers and puts the 32-bit integer result in LO and the remainder in HI.
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| |-
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| |rowspan=14| Data Transfer
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| |-
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| | Load word || lw $t,C($s) || $t = Memory[$s + C] || I || 23<sub>16</sub> || - || loads the word stored from: MEM[$s+C] and the following 3 bytes.
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| |-
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| | Load halfword || lh $t,C($s) || $t = Memory[$s + C] (signed) || I || 21<sub>16</sub> || - || loads the halfword stored from: MEM[$s+C] and the following byte. Sign is extended to width of register.
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| |-
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| | Load halfword unsigned || lhu $t,C($s) || $t = Memory[$s + C] (unsigned) || I || 25<sub>16</sub> || - || As above without [[sign extension]].
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| |-
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| | Load byte || lb $t,C($s) || $t = Memory[$s + C] (signed) || I || 20<sub>16</sub> || - || loads the byte stored from: MEM[$s+C].
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| |-
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| | Load byte unsigned || lbu $t,C($s) || $t = Memory[$s + C] (unsigned) || I || 24<sub>16</sub> || - || As above without sign extension.
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| |-
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| | Store word || sw $t,C($s) || Memory[$s + C] = $t || I || 2B<sub>16</sub> || - || stores a word into: MEM[$s+C] and the following 3 bytes. The order of the operands is a large source of confusion.
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| |-
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| | Store half || sh $t,C($s) || Memory[$s + C] = $t || I || 29<sub>16</sub> || - || stores the least-significant 16-bit of a register (a halfword) into: MEM[$s+C].
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| |-
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| | Store byte || sb $t,C($s) || Memory[$s + C] = $t || I || 28<sub>16</sub> || - || stores the least-significant 8-bit of a register (a byte) into: MEM[$s+C].
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| |-
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| | Load upper immediate || lui $t,C || $t = C << 16 || I || F<sub>16</sub> || - || loads a 16-bit immediate operand into the upper 16-bits of the register specified. Maximum value of constant is 2<sup>16</sup>-1
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| |-
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| | Move from high || mfhi $d || $d = HI || R || 0 || 10<sub>16</sub> || Moves a value from HI to a register. Do not use a multiply or a divide instruction within two instructions of mfhi (that action is undefined because of the MIPS pipeline).
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| |-
| |
| | Move from low || mflo $d || $d = LO || R || 0 || 12<sub>16</sub> || Moves a value from LO to a register. Do not use a multiply or a divide instruction within two instructions of mflo (that action is undefined because of the MIPS pipeline).
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| |-
| |
| | Move from Control Register || mfcZ $t, $d || $t = Coprocessor[Z].ControlRegister[$d] || R || 0 || || Moves a 4 byte value from Coprocessor Z Control register to a general purpose register. Sign extension.
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| |-
| |
| | Move to Control Register || mtcZ $t, $d || Coprocessor[Z].ControlRegister[$d] = $t || R || 0 || || Moves a 4 byte value from a general purpose register to a Coprocessor Z Control register. Sign extension.
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| |-
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| |rowspan=8| Logical
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| ||And || and $d,$s,$t || $d = $s & $t || R || 0 || 24<sub>16</sub> || [[Bitwise operation|Bitwise]] and<br><pre>000000ss sssttttt ddddd--- --100100</pre>
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| |-
| |
| | And immediate || andi $t,$s,C || $t = $s & C || I || C<sub>16</sub> || - || Leftmost 16 bits are padded with 0s<br><pre>001100ss sssttttt CCCCCCCC CCCCCCCC</pre>
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| |-
| |
| | Or || or $d,$s,$t || $d = $s | $t || R || 0 || 25<sub>16</sub> || [[Bitwise operation|Bitwise]] or
| |
| |-
| |
| | Or immediate || ori $t,$s,C || $t = $s | C || I || D<sub>16</sub> || - || Leftmost 16 bits are padded with 0s
| |
| |-
| |
| | Exclusive or || xor $d,$s,$t || $d = $s ^ $t || R || 0 || 26<sub>16</sub> ||
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| |-
| |
| | Nor || nor $d,$s,$t || $d = ~ ($s | $t) || R || 0 || 27<sub>16</sub> || [[Bitwise operation|Bitwise]] nor
| |
| |-
| |
| | Set on less than || slt $d,$s,$t || $d = ($s < $t) || R || 0 || 2A<sub>16</sub> || Tests if one register is less than another.
| |
| |-
| |
| | Set on less than immediate || slti $t,$s,C || $t = ($s < C) || I || A<sub>16</sub> || - || Tests if one register is less than a constant.
| |
| |-
| |
| |rowspan=6| Bitwise Shift
| |
| || Shift left logical immediate || sll $d,$t,shamt || $d = $t << shamt || R || 0 || 0 || shifts shamt number of bits to the left (multiplies by <math>2^{shamt} </math>)
| |
| |-
| |
| | Shift right logical immediate || srl $d,$t,shamt || $d = $t >> shamt || R || 0 || 2<sub>16</sub> || shifts shamt number of bits to the right - zeros are shifted in (divides by <math>2^{shamt} </math>). Note that this instruction only works as division of a two's complement number if the value is positive.
| |
| |-
| |
| | Shift right arithmetic immediate || sra $d,$t,shamt || <math>$d = $t >> shamt + \left(\sum_{n=1}^{\text{shamt}}2^{32-n}\right)\cdot \left($t>>31\right)</math> || R || 0 || 3<sub>16</sub> || shifts shamt number of bits - the sign bit is shifted in (divides [[two's complement|2's complement number]] by <math>2^{shamt} </math>)
| |
| |-
| |
| || Shift left logical || sllv $d,$t,$s || $d = $t << $s || R || 0 || 4 <sub>16</sub> || shifts $s number of bits to the left (multiplies by <math>2^{$s} </math>)
| |
| |-
| |
| | Shift right logical || srlv $d,$t,$s || $d = $t >> $s || R || 0 || 6<sub>16</sub> || shifts $s number of bits to the right - zeros are shifted in (divides by <math>2^{$s} </math>). Note that this instruction only works as division of a two's complement number if the value is positive.
| |
| |-
| |
| | Shift right arithmetic || srav $d,$t,$s || <math>$d = $t >> $s + \left(\sum_{n=1}^{$\text{s}}2^{32-n}\right)\cdot \left($t>>31\right)</math> || R || 0 || 7<sub>16</sub> || shifts $s number of bits - the sign bit is shifted in (divides [[two's complement|2's complement number]] by <math>2^{$s} </math>)
| |
| |-
| |
| |rowspan=2| Conditional branch
| |
| || Branch on equal || beq $s,$t,C || if ($s == $t) go to PC+4+4*C || I || 4<sub>16</sub> || - || Goes to the instruction at the specified address if two registers are equal.<br><pre>000100ss sssttttt CCCCCCCC CCCCCCCC</pre>
| |
| |-
| |
| | Branch on not equal || bne $s,$t,C || if ($s != $t) go to PC+4+4*C || I || 5<sub>16</sub> || - || Goes to the instruction at the specified address if two registers are ''not'' equal.
| |
| |-
| |
| |rowspan=3| Unconditional jump
| |
| || Jump || j C || PC = PC+4[31:28] . C*4 || J || 2<sub>16</sub> || - || Unconditionally jumps to the instruction at the specified address.
| |
| |-
| |
| | Jump register || jr $s || goto address $s || R || 0 || 8<sub>16</sub> || Jumps to the address contained in the specified register
| |
| |-
| |
| | Jump and link || jal C || $31 = PC + 4; PC = PC+4[31:28] . C*4 || J || 3<sub>16</sub> || - || For procedure call - used to call a subroutine, $31 holds the return address; returning from a subroutine is done by: jr $31. Return address is PC + 8, not PC + 4 due to the use of a branch [[delay slot]] which forces the instruction after the jump to be executed
| |
| |}
| |
| | |
| Note: In MIPS assembly code, the offset for branching instructions can be represented by a label elsewhere in the code.
| |
| | |
| Note: There is no corresponding ''load lower immediate'' instruction; this can be done by using addi (add immediate, see below) or ori (or immediate) with the register $0 (whose value is always zero). For example, both <code>addi $1, $0, 100</code> and <code>ori $1, $0, 100</code> load the decimal value 100 into register $1.
| |
| | |
| Note: Subtracting an immediate can be done with adding the negation of that value as the immediate.
| |
| | |
| ===Floating point===
| |
| MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair.
| |
| {| class=wikitable
| |
| |-
| |
| !Category !! Name !! Instruction syntax !! Meaning !!colspan=3| Format/opcode/funct !! Notes/Encoding
| |
| |-
| |
| |rowspan=8| Arithmetic
| |
| ||FP add single || add.s $x,$y,$z || $x = $y + $z || || || || Floating-Point add (single precision)
| |
| |-
| |
| | FP subtract single || sub.s $x,$y,$z || $x = $y - $z || || || || Floating-Point subtract (single precision)
| |
| |-
| |
| | FP multiply single || mul.s $x,$y,$z || $x = $y * $z || || || || Floating-Point multiply (single precision)
| |
| |-
| |
| | FP divide single || div.s $x,$y,$z || $x = $y / $z || || || || Floating-Point divide (single precision)
| |
| |-
| |
| | FP add double || add.d $x,$y,$z || $x = $y + $z || || || || Floating-Point add (double precision)
| |
| |-
| |
| | FP subtract double || sub.d $x,$y,$z || $x = $y - $z || || || || Floating-Point subtract (double precision)
| |
| |-
| |
| | FP multiply double || mul.d $x,$y,$z || $x = $y * $z || || || || Floating-Point multiply (double precision)
| |
| |-
| |
| | FP divide double || div.d $x,$y,$z || $x = $y / $z || || || || Floating-Point divide (double precision)
| |
| |-
| |
| |rowspan=2| Data Transfer
| |
| || Load word coprocessor || lwcZ $x,CONST ($y) || Coprocessor[Z].DataRegister[$x] = Memory[$y + CONST] || I || || || Loads the 4 byte word stored from: MEM[$y+CONST] into a Coprocessor data register. Sign extension.
| |
| |-
| |
| | Store word coprocessor || swcZ $x,CONST ($y) || Memory[$y + CONST] = Coprocessor[Z].DataRegister[$x]|| I || || || Stores the 4 byte word held by a Coprocessor data register into: MEM[$y+CONST]. Sign extension.
| |
| |-
| |
| |rowspan=2| Logical
| |
| || FP compare single (eq,ne,lt,le,gt,ge) || c.lt.s $f2,$f4 || if ($f2 < $f4) cond=1; else cond=0 || || || || Floating-point compare less than single precision
| |
| |-
| |
| |FP compare double (eq,ne,lt,le,gt,ge) || c.lt.d $f2,$f4 || if ($f2 < $f4) cond=1; else cond=0 || || || || Floating-point compare less than double precision
| |
| |-
| |
| |rowspan=2| Branch
| |
| || branch on FP true || bc1t 100 || if (cond == 1) go to PC+4+100 || || || || PC relative branch if FP condition
| |
| |-
| |
| | branch on FP false || bc1f 100 || if (cond == 0) go to PC+4+100 || || || || PC relative branch if not condition
| |
| |}
| |
| | |
| ===Pseudo instructions===
| |
| | |
| These instructions are accepted by the MIPS assembler, although they are not real instructions within the MIPS instruction set. Instead, the assembler translates them into sequences of real instructions.
| |
| | |
| {| class=wikitable
| |
| |-
| |
| ! Name !! instruction syntax !! Real instruction translation !! meaning
| |
| |-
| |
| | Move || move $rt,$rs || add $rt,$rs,$zero || R[rt]=R[rs]
| |
| |-
| |
| | Clear || clear $rt || add $rt,$zero,$zero || R[rt]=0
| |
| |-
| |
| | Not || not $rt, $rs || nor $rt, $rs, $zero || R[rt]=~R[rs]
| |
| |-
| |
| | Load Address || la $rd, LabelAddr || lui $rd, LabelAddr[31:16]; ori $rd,$rd, LabelAddr[15:0] || $rd = Label Address
| |
| |-
| |
| | Load Immediate || li $rd, IMMED[31:0] || lui $rd, IMMED[31:16]; ori $rd,$rd, IMMED[15:0] || $rd = 32 bit Immediate value
| |
| |-
| |
| | Branch unconditionally || b Label || beq $zero,$zero,Label || PC=Label
| |
| |-
| |
| | Branch and link || bal Label || bgezal $zero,Label || R[31]=PC+8; PC=Label
| |
| |-
| |
| | Branch if greater than || bgt $rs,$rt,Label || slt $at,$rt,$rs; bne $at,$zero,Label || if(R[rs]>R[rt]) PC=Label
| |
| |-
| |
| | Branch if less than || blt $rs,$rt,Label || slt $at,$rs,$rt; bne $at,$zero,Label || if(R[rs]<R[rt]) PC=Label
| |
| |-
| |
| | Branch if greater than or equal || bge $rs,$rt,Label || slt $at,$rs,$rt; beq $at,$zero,Label || if(R[rs]>=R[rt]) PC=Label
| |
| |-
| |
| | Branch if less than or equal || ble $rs,$rt,Label || slt $at,$rt,$rs; beq $at,$zero,Label || if(R[rs]<=R[rt]) PC=Label
| |
| |-
| |
| | Branch if greater than unsigned || bgtu $rs,$rt,Label || sltu $at,$rt,$rs; bne $at,$zero,Label || if(R[rs]>R[rt]) PC=Label
| |
| |-
| |
| | Branch if greater than zero || bgtz $rs,Label || slt $at,$zero,$rs; bne $at,$zero,Label || if(R[rs]>0) PC=Label
| |
| |-
| |
| | Branch if equal to zero || beqz $rs,Label || beq $rs,$zero,Label || if(R[rs]==0) PC=Label
| |
| |-
| |
| | Multiplies and returns only first 32 bits || mul $d, $s, $t || mult $s, $t; mflo $d || $d = $s * $t
| |
| |-
| |
| | Divides and returns quotient || div $d, $s, $t || div $s, $t; mflo $d || $d = $s / $t
| |
| |-
| |
| | Divides and returns remainder || rem $d, $s, $t || div $s, $t; mfhi $d || $d = $s % $t
| |
| |}
| |
| | |
| === Other instructions ===
| |
| * [[NOP]] (no operation) (machine code 0x00000000, interpreted by CPU as <code>sll $0,$0,0</code>)
| |
| * break (breaks the program, used by debuggers)
| |
| * syscall (used for system calls to the operating system)
| |
| | |
| == Compiler register usage ==
| |
| {{main|Calling convention#MIPS}}
| |
| | |
| The hardware architecture specifies that:
| |
| * General purpose register $0 always returns a value of 0.
| |
| * General purpose register $31 is used as the link register for jump and link instructions.
| |
| * HI and LO are used to access the multiplier/divider results, accessed by the mfhi (move from high) and mflo commands.
| |
| These are the only hardware restrictions on the usage of the general purpose registers.
| |
| | |
| The various MIPS tool-chains implement specific calling conventions that further restrict how
| |
| the registers are used. These [[calling convention]]s are totally maintained by the tool-chain software
| |
| and are not required by the hardware.
| |
| | | |
| {| class="wikitable"
| | </ul> |
| |+ '''Registers for O32 Calling Convention'''
| |
| ! Name || Number || Use || Callee must preserve?
| |
| |-
| |
| ! $zero
| |
| | $0 || constant 0 || {{N/A}}
| |
| |-
| |
| ! $at
| |
| | $1 || assembler temporary || {{no}}
| |
| |-
| |
| ! $v0–$v1
| |
| | $2–$3 || values for function returns and expression evaluation || {{no}}
| |
| |-
| |
| ! $a0–$a3
| |
| | $4–$7 || function arguments || {{no}}
| |
| |-
| |
| ! $t0–$t7
| |
| | $8–$15 || temporaries || {{no}}
| |
| |-
| |
| ! $s0–$s7
| |
| | $16–$23 || saved temporaries || {{yes}}
| |
| |-
| |
| ! $t8–$t9
| |
| | $24–$25 || temporaries || {{no}}
| |
| |-
| |
| ! $k0–$k1
| |
| | $26–$27 || reserved for OS kernel || {{N/A}}
| |
| |-
| |
| ! $gp
| |
| | $28 || global pointer || {{yes}}
| |
| |-
| |
| ! $sp
| |
| | $29 || [[Stack-based memory allocation|stack pointer]] || {{yes}}
| |
| |-
| |
| ! $fp
| |
| | $30 || [[frame pointer]] || {{yes}}
| |
| |-
| |
| ! $ra
| |
| | $31 || [[return statement|return address]] || {{N/A}}
| |
| |}
| |
| | |
| {| class="wikitable"
| |
| |+ '''Registers for N32 and N64 Calling Conventions<ref>ftp://ftp.linux-mips.org/pub/linux/mips/doc/ABI2/MIPS-N32-ABI-Handbook.pdf</ref>'''
| |
| ! Name || Number || Use || Callee must preserve?
| |
| |-
| |
| ! $zero
| |
| | $0 || constant 0 || {{N/A}}
| |
| |-
| |
| ! $at
| |
| | $1 || assembler temporary || {{no}}
| |
| |-
| |
| ! $v0–$v1
| |
| | $2–$3 || values for function returns and expression evaluation || {{no}}
| |
| |-
| |
| ! $a0–$a7
| |
| | $4–$11 || function arguments || {{no}}
| |
| |-
| |
| ! $t4–$t7
| |
| | $12–$15 || temporaries || {{no}}
| |
| |-
| |
| ! $s0–$s7
| |
| | $16–$23 || saved temporaries || {{yes}}
| |
| |-
| |
| ! $t8–$t9
| |
| | $24–$25 || temporaries || {{no}}
| |
| |-
| |
| ! $k0–$k1
| |
| | $26–$27 || reserved for OS kernel || {{N/A}}
| |
| |-
| |
| ! $gp
| |
| | $28 || global pointer || {{yes}}
| |
| |-
| |
| ! $sp
| |
| | $29 || [[Stack-based memory allocation|stack pointer]] || {{yes}}
| |
| |-
| |
| ! $s8
| |
| | $30 || [[frame pointer]] || {{yes}}
| |
| |-
| |
| ! $ra
| |
| | $31 || [[return statement|return address]] || {{N/A}}
| |
| |}
| |
| | |
| Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. For example, $s-registers must be saved to the stack by a procedure that needs to use them, and $sp and $fp are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast, $ra is changed automatically by any normal function call (ones that use jal), and $t-registers must be saved by the program before any procedure call (if the program needs the values inside them after the call).
| |
| | |
| == Simulators ==
| |
| Open Virtual Platforms (OVP)<ref>{{cite web|url=http://www.OVPworld.org |title=OVP: Fast Simulation, Free Open Source Models. Virtual Platforms for software development |publisher=Ovpworld.org |date= |accessdate=2012-05-30}}</ref> includes the freely available for non-commercial use simulator [[OVPsim]], a library of models of processors, peripherals and platforms, and APIs which enable users to develop their own models. The models in the library are open source, written in C, and include the MIPS 4K, 24K, 34K, 74K, 1004K, 1074K, M14K, microAptiv, interAptiv, proAptiv 32 bit cores and the MIPS 64bit 5K range of cores. These models are created and maintained by Imperas<ref>{{cite web|url=http://www.imperas.com |title=Imperas |publisher=Imperas |date=2008-03-03 |accessdate=2012-05-30}}</ref> and in partnership with MIPS Technologies have been tested and assigned the MIPS-Verified (tm) mark. Sample MIPS-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images. These platforms–emulators are available as source or binaries and are fast, free for non-commercial usage, and are easy to use. [[OVPsim]] is developed and maintained by [[Imperas]] and is very fast (hundreds of million of instructions per second), and built to handle multicore homogeneous and heterogeneous architectures and systems.
| |
| | |
| There is a freely available MIPS32 simulator (earlier versions simulated only the R2000/R3000) called [[SPIM]] for use in education. EduMIPS64<ref>{{cite web|url=http://www.edumips.org |title=EduMIPS64 |publisher=Edumips.org |date= |accessdate=2012-05-30}}</ref> is a GPL graphical cross-platform MIPS64 CPU simulator, written in Java/Swing. It supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run by the CPU. It has educational purposes and is used in some{{Who|date=March 2009}} computer architecture courses in universities around the world.
| |
| | |
| MARS<ref>{{cite web|url=http://courses.missouristate.edu/KenVollmar/MARS/ |title=MARS MIPS simulator - Missouri State University |publisher=Courses.missouristate.edu |date= |accessdate=2012-05-30}}</ref> is another GUI-based MIPS emulator designed for use in education, specifically for use with Hennessy's ''Computer Organization and Design''.
| |
| | |
| WebMIPS<ref>http://www.maiconsoft.com.br/webmips/index.asp (online demonstration) http://www.dii.unisi.it/~giorgi/WEBMIPS/ (source)</ref> is a browser based MIPS simulator with visual representation of a generic, pipelined processor. This simulator is quite useful for register tracking during step by step execution.
| |
| | |
| More advanced free emulators are available from the [[GXemul]] (formerly known as the mips64emul project) and [[QEMU]] projects. These emulate the various MIPS III and IV microprocessors in addition to entire computer systems which use them.
| |
| | |
| Commercial simulators are available especially for the embedded use of MIPS processors, for example Wind River [[Simics]] (MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000, Broadcom/Netlogic ec4400, [[Cavium]] Octeon I), [[Imperas]] (all MIPS32 and MIPS64 cores), VaST Systems (R3000, R4000), and [[CoWare]] (the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K).
| |
| | |
| ==See also==
| |
| * [[DLX]], a very similar architecture designed by [[John L. Hennessy]] (creator of MIPS) for teaching purposes
| |
| * [[MIPS-X]], developed as a follow-on project to the MIPS architecture
| |
| | |
| ==References==
| |
| {{reflist|30em}}
| |
| | |
| == Further reading ==
| |
| *{{cite book|first=David A|last=Patterson|authorlink=David A. Patterson (scientist)|coauthors=[[John L. Hennessy]]|title=Computer Organization and Design: The Hardware/Software Interface|publisher=[[Morgan Kaufmann Publishers]]|isbn=1-55860-604-1}}
| |
| *{{cite book|first=Dominic|last=Sweetman|title=See MIPS Run, 2nd edition|publisher=Morgan Kaufmann Publishers|isbn=0-12-088421-6}}
| |
| *{{cite book|first=Dominic|last=Sweetman|title=See MIPS Run|publisher=Morgan Kaufmann Publishers|isbn=1-55860-410-3}}
| |
| *{{cite book|first=Erin|last=Farquhar|coauthors=Philip Bunce|title=MIPS Programmer's Handbook|publisher=Morgan Kaufmann Publishers|isbn=1-55860-297-6}}
| |
| | |
| ==External links==
| |
| {{Wikibooks|MIPS Assembly}}
| |
| * [http://imgtec.com Imagination Technologies]
| |
| * [http://www.imgtec.com/mips/developers/ MIPS Developers] at [[Imagination Technologies]]
| |
| * [http://www.imgtec.com/mips/mips-architectures.asp MIPS Architectures] at [[Imagination Technologies]]
| |
| * [http://www.cs.wisc.edu/~larus/HP_AppA.pdf Patterson & Hennessy - Appendix A]
| |
| * [http://logos.cs.uic.edu/366/notes/MIPS%20Quick%20Tutorial.htm Summary of MIPS assembly language]
| |
| * [http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html MIPS Instruction reference]
| |
| * [http://courses.missouristate.edu/KenVollmar/MARS/ MARS (MIPS Assembler and Runtime Simulator)]
| |
| * [http://www.cpu-collection.de/?tn=1&l0=cl&l1=MIPS%20Rx000 MIPS processor images and descriptions at cpu-collection.de]
| |
| * [http://chortle.ccsu.edu/AssemblyTutorial/index.html A programmed introduction to MIPS assembly]
| |
| * [http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Mips/bitshift.html Mips bitshift operators]
| |
| * [http://www.it.uu.se/edu/course/homepage/datsystDV/ht04/Project/tools/machinedata/4KcProgMan.pdf MIPS software user's manual]
| |
| * [http://meld.org/library/education/mips-architectures MIPS Architecture history diagram]
| |
| | |
| {{RISC-based processor architectures}}
| |
| {{Microcontrollers}}
| |
| {{MIPS microprocessors}}
| |
| | |
| {{use dmy dates|date=January 2012}}
| |
| | |
| {{DEFAULTSORT:Mips Architecture}}
| |
| [[Category:1981 introductions]]
| |
| [[Category:Advanced RISC Computing]]
| |
| [[Category:Instruction set architectures]]
| |
| [[Category:MIPS Technologies]]
| |