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| Dual [[Electrical impedance|impedance]] and dual network are terms used in [[Network analysis (electronics)|electronic network analysis]]. The dual of an impedance <math>Z\,\!</math> is its algebraic inverse <math>Z'=\frac{1}{Z}</math>. Note that <math>Z\,</math> and <math>Z'\,</math> are the duals of each other, that is, they are reciprocal. For this reason the dual impedance is also called the inverse impedance. The dual of a network of impedances is that network whose impedance is <math>Z'\,\!</math>. In the case of a network with more than one [[Two-port network|port]] the impedance looking into each of the ports must simultaneously be dual.<br /><br />
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| Another way of stating this is that the dual of <math>Z\,\!</math> is the admittance <math>Y=Z\,\!</math>.<br /><br />
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| This is consistent with the [[Duality (electrical circuits)|definition of dual]] as being that circuit whose voltages and currents are interchanged since <math>Z=\frac{V}{I}</math> and <math>Z'=\frac{1}{Z}=\frac{I}{V}</math><ref>Ghosh, pp.50-51</ref><br /><br />
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| __TOC__
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| {{Complex Z}}
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| ==Scaled and normalised duals==
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| In a real design situation it is usually desired to find the dual of an impedance with respect to some nominal or [[characteristic impedance]]. To do this, Z and Z' are scaled to the nominal impedance Z<sub>0</sub> so that;
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| <math>\frac{Z'}{Z_0}=\frac{Z_0}{Z}</math> | |
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| Z<sub>0</sub> is usually taken to be a purely real number R<sub>0</sub>, so Z' is only changed by a real factor of R<sub>0</sub><sup>2</sup>. In other words, the dual remains qualitatively the same circuit but all the component values must be scaled quantitively by R<sub>0</sub><sup>2</sup>.<ref>Redifon, p.44</ref> The scaling factor R<sub>0</sub><sup>2</sup>. has the dimensions of Ω<sup>2</sup>. From this it follows that the constant 1 in the unscaled expression also needs to be assigned the dimensions Ω<sup>2</sup> in any [[dimensional analysis]].
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| ==Duals of basic circuit elements==
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| {| class="wikitable" style="text-align:center;"
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| |+<ref>Guillemin, pp.535-539</ref>
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| ! Element
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| ! Z
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| ! Dual
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| ! Z'
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| | [[File:Dual Z 1.PNG|thumb|left|Resistor R]]
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| | <math> R\,\!</math>
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| | [[File:Dual Z 2.PNG|thumb|left|Conductor G = R]]
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| | <math>\frac{1}{R}</math>
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| | [[File:Dual Z 2.PNG|thumb|left|Conductor G]]
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| | <math>\frac{1}{G}</math>
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| | [[File:Dual Z 1.PNG|thumb|left|Resistor R = G]]
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| | <math> G\,\!</math>
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| | [[File:Dual Z 3.PNG|thumb|left|Inductor L]]
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| | <math> i\omega L\,\!</math>
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| | [[File:Dual Z 4.PNG|thumb|left|Capacitor C = L]]
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| | <math> \frac{1}{i\omega L}</math>
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| | [[File:Dual Z 4.PNG|thumb|left|Capacitor C]]
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| | <math> \frac {1}{i\omega C}</math>
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| | [[File:Dual Z 3.PNG|thumb|left|Inductor L = C]]
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| | <math> i\omega C\,\!</math>
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| | [[File:Dual Z 5.PNG|thumb|left|Series impedances Z = Z<sub>1</sub> + Z<sub>2</sub>]]
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| | <math> Z_1 + Z_2\,\!</math>
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| | [[File:Dual Z 6.PNG|thumb|left|Parallel admittances Y = Z<sub>1</sub> + Z<sub>2</sub>]]
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| | <math> \frac {1}{Z_1 + Z_2}</math>
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| | [[File:Dual Z 6.PNG|thumb|left|Parallel impedances 1/Z = 1/Z<sub>1</sub> + 1/Z<sub>2</sub>]]
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| | <math> Z = \frac{Z_1 Z_2}{Z_1 + Z_2}</math>
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| | [[File:Dual Z 5.PNG|thumb|left|Series admittances 1/Y = 1/Z<sub>1</sub> + 1/Z<sub>2</sub>]]
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| | <math> \frac {1}{Z_1} + \frac{1}{Z_2}</math>
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| | [[File:Dual Z 7.PNG|thumb|left|Voltage generator V]]
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| | [[File:Dual Z 8.PNG|thumb|left|Current generator I = V]]
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| | [[File:Dual Z 8.PNG|thumb|left|Current generator I]]
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| | [[File:Dual Z 7.PNG|thumb|left|Voltage generator V = I]]
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| |}
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| ==Graphical method==
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| There is a graphical method of obtaining the dual of a network which is often easier to use than the mathematical expression for the impedance. Starting with a circuit diagram of the network in question, Z, the following steps are drawn on the diagram to produce Z' superimposed on top of Z. Typically, Z' will be drawn in a different colour to help distinguish it from the original, or, if using [[CAD]], Z' can be drawn on a different layer.
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| #A generator is connected to each [[Two-port network|port]] of the original network. The purpose of this step is to prevent the ports from being "lost" in the inversion process. This happens because a port left open circuit will transform into a short circuit and disappear.
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| #A dot is drawn at the centre of each [[Mesh analysis|mesh]] of the network Z. These dots will become the circuit [[Node (circuits)|nodes]] of Z'.
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| #A conductor is drawn which entirely encloses the network Z. This conductor also becomes a node of Z'.
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| #For each circuit element of Z, its dual is drawn between the nodes in the centre of the meshes either side of Z. Where Z is on the edge of the network, one of these nodes will be the enclosing conductor from the previous step.<ref>Guillemin, pp.49-52<br/>Suresh, pp.516-517</ref>
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| This completes the drawing of Z'. This method also serves to demonstrate that the dual of a mesh transforms into a node and the dual of a node transforms into a mesh. Two useful examples are given below, both to illustrate the process and to give some further examples of dual networks.
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| ===Example - star network===
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| {|
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| |[[File:Graphic method 1.svg|thumb|left|200px|A star network of [[inductor]]s, such as might be found on a [[three-phase]] [[transformer]]]]
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| |[[File:Graphic method 2.svg|thumb|none|200px|Attaching generators to the three ports]]
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| |[[File:Graphic method 3.svg|thumb|left|200px|Nodes of the dual network]]
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| |[[File:Graphic method 4.svg|thumb|none|200px|Components of the dual network]]
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| |[[File:Graphic method 5.svg|thumb|left|200px|The dual network with the original removed and slightly redrawn to make the topology clearer]]
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| |[[File:Graphic method 6.svg|thumb|none|200px|The dual network with the notional generators removed]]
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| |}
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| It is now clear that the dual of a star network of inductors is a delta network of [[capacitor]]s. This dual circuit is not the same thing as a star-delta (Y-Δ) transformation. A [[Y-Δ transform]] results in an [[equivalent circuit|''equivalent'' circuit]], not a dual circuit.
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| ===Example - Cauer network===
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| Filters designed using [[Cauer topology (electronics)|Cauer's topology]] of the first form are [[low-pass]] filters consisting of a [[ladder network]] of series inductors and [[Shunt (electrical)#Use in electronic filter circuits|shunt]] capacitors.
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| [[File:Graphic method 7.svg|thumb|left|350px|A low-pass filter implemented in Cauer topology]]
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| [[File:Graphic method 8.svg|thumb|none|350px|Attaching generators to the input and output ports]]
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| [[File:Graphic method 9.svg|thumb|left|350px|Nodes of the dual network]]
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| [[File:Graphic method 10.svg|thumb|none|350px|Components of the dual network]]
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| [[File:Graphic method 11.svg|thumb|left|350px|The dual network with the original removed and slightly redrawn to make the topology clearer]]
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| <br style="clear:both;"/> | |
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| It can now be seen that the dual of a Cauer low-pass filter is still a Cauer low-pass filter. It does not transform into a [[high-pass]] filter as might have been expected. Note, however, that the first element is now a shunt component instead of a series component.
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| ==See also==
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| * [[Topology (electrical circuits)]]
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| ==References==
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| {{reflist}}
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| ==Bibliography==
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| *''Redifon Radio Diary, 1970'', pp. 45–48, William Collins Sons & Co, 1969.
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| *Ghosh, Smarajit, ''Network Theory: Analysis and Synthesis'', Prentice Hall of India
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| *Guillemin, Ernst A., ''Introductory Circuit Theory'', New York: John Wiley & Sons, 1953 {{OCLC|535111}}
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| *Suresh, Kumar K. S., "Introduction to network topology" chapter 11 in ''Electric Circuits And Networks'', Pearson Education India, 2010 ISBN 81-317-5511-8.
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| [[Category:Analog circuits]]
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| [[Category:Filter theory]]
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| [[Category:Electronic design]]
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Jump in and began right away. Don't wait for the people the planets to maintain perfect alignment before you begin. Don't for you to all those negative individuals your the life. If you your own research MLM business will never happen.
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